1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating high-voltage lateral double-diffused metal oxide semiconductor (LDMOS).
2. Description of the Related Art
Due to the increasing number of semiconductor elements incorporated in integrated circuits, the size of metal oxide semiconductor (MOS) components needs to be decreased. Accordingly, as the channel length of the MOS is decreased, the operating speed is increased. However, there is an increased likelihood of a problem, referred to as "short channel effect", caused by the reduced channel length. If the voltage level is fixed, according to the equation of electrical field =electrical voltage/channel length, as the channel length is shortened, the strength of electrical field is increased. Thus, as the strength of electrical field increases, energy of electron increases and electrical breakdown is likely to occur.
In general, a high voltage is on an order of about 8 vol or above. A MOS that can be operated under high voltage is called a high-voltage MOS. An isolation layer and a drift region below the isolation layer are used to increase the distance between the source/drain and the gate electrode in the high-voltage MOS. Thus, the MOS is able to work normally under the high voltage.
FIG. 1 is a schematic, cross-sectional view of a conventional LDMOS.
In FIG. 1, a conventional LDMOS including a P-type silicon substrate 100, a field oxide layer 101, a gate oxide layer 102, a gate layer 103, a N.sup.+ drain region 104, an N.sup.- drift region 105, an N.sup.+ source region 106, a P-doped region 107, and a P.sup.+ -doped region 108.
In the conventional LDMOS, the drift region 105 is under the crossing wire 109. While operating the conventional LDMOS under high voltage, high electrical field crowding occurs at the junction 110 between the drift region 105 and the channel. Thus, the breakdown voltage is decreased.